In a digital system having a CPU and a storage device for example, pulses or digital signals are affected by the reflected waves of the signals at terminal ends of a transmission line (referred to as bus) when the frequencies of the signals are high and the bus is fairly long. The reflected waves distort the waveforms of the pulses.
For instance, a digital signal having a pulse repetition frequency of 100 MHz or above can be deformed into a stepping pulse when the transmission time of a bus exceeds one fifth of the rise time of the pulse. Such deformation of pulse will greatly affect the threshold time of the digital signal. In particular, this tendency becomes significant when the pulse repetition frequency is 200 MHz or above and the length of the bus exceeds 200 mm.
In order to suppress the influence of the reflective waves, a terminal resistor is inserted at the starting point or the terminal point, or both, of the bus so that the resistance of the terminal resistor matches the characteristic impedance of the bus, thereby suppressing the reflective energy of waves.
In recent years, CPUs, input/output (I/O) devices, and storage devices have become increasingly faster. Some of them have operating frequencies on the order of 1 GHz. Such speed up of CPUs will continue still.
Thus, in view of these high speed CPUs and devices, what is needed is a bus which can ensure transmission of a high frequency digital signal to and from these CPUs and devices.
Use of terminal resistors has been known over the last 20 years in the art of emitter coupled logic (ECL) circuit of a main frame for example, to suppress the reflection of waves. This approach has been frequently used also in CMOS circuits to deal with high speed storage devices.
A pulse signal includes a fundamental frequency which is a given repetition frequency of the pulse, and additional higher harmonics superposed on the fundamental mode. Thus, in the design of a bus, it is necessary to take account of waves having frequencies greater than the fundamental mode by one order.
It is also important to know that in actuality a pulse has a finite rise time Tr to rise from the base voltage to the peak voltage, and a finite fall time Tf to fall from the peak voltage to the base voltage. Thus, the pulse has an apparent transition time Tr plus Tf, and hence an apparent frequency ft associated with the apparent transition time. The apparent frequency ft is theoretically given byft=½πRCwhere RC is a time constant of n integration.The frequency ft is modified by an empirical conversion formula;ft=0.35/Trwhere Tr is given byTr=2.2 RC.Normally, the value of Tr is set to the period for the pulse to achieve 10 to 90% of the peak value. Thus, Tr is multiplied by 0.8 when it is evaluated.
A terminal resistor supposedly has a resistance that matches the characteristic impedance of the bus to minimize the reflection of the waves in the bus. In actuality, however, in addition to the pure resistance, the terminal resistor has a reactance due to a parasitic inductance and a parasitic capacitance that are structurally created in the terminal resistor.
Hence, in order to suppress the reflection of waves by a terminal resistor, it is necessary to take account of the reactance of the terminal resistor itself along with the higher harmonics and the apparent frequency associated with the transition time of the pulse.
FIGS. 1A–3B show simulated circuits of a terminal resistor under different conditions. The figures also show the results of the simulations.
FIG. 1A illustrates a simulatory terminal resistor having a resistance of 50 Ω, coupled with parasitic inductance L1 of 1 nH, and parasitic capacitance C1 of 10 pF. The resistor is connected to the terminal end of a bus T1 having a characteristic impedance Zo=50 Ω. The transmission delay time Tpd is 1.5 ns (which amounts to a length of 100 mm on a printed wiring substrate), as shown in FIG. 1A. In the example shown herein, it is assumed that the terminal resistor is an ordinary chip resistor having average characteristics.
In operation, the bus T1 is supplied with a pulse “i” having a base voltage V1=0 Volt, peak voltage V2=3.3 Volts, rise time Tr=5 ns, fall time Tf=5 ns, pulse width Pw=20 ns, and a pulse period Per=50 ns. The repetition frequency f is assumed to be 20 MHz. The apparent frequency ft is determined from the transition time byft=0.35/(5 ns×0.8)≈100 MHz.The output waveform “ii” is measured at the terminal end of the bus T1, as shown.
FIG. 1B compares the input and output waveforms “i” and “ii”, respectively. Although the output waveform “ii” overshoots a little, it has a good waveform. Thus, it is seen that the bus can satisfactorily transmit pulses having an apparent frequency of 100 MHz and repetition frequency f of 20 MHz.
FIG. 2A shows a simulation in which the same bus T1 is terminated with the same terminal resistor as in FIG. 1A. In operation, the bus T1 is supplied with a pulse “i” having a base voltage V1=0 Volt, peak voltage V2=3.3 Volts, rise time Tr=0.5 ns, fall time Tf=0.5 ns, pulse width Pw=2 ns, and pulse period Per=5 ns. The repetition frequency f of the pulse is 200 MHz. The apparent frequency ft is determined from the transition time byft=0.35/(0.5 ns×0.8)≈1 GHz.The output waveform “ii” is measured at the terminal end of the bus T1.
FIG. 2B compares the input waveform “i” with the resultant output waveform “ii”. It is seen in FIG. 2 that the output waveforms “ii” is delayed from the input waveform “i” by the transmission delay time Tpd (1.5 ns) and that the output waveform “ii” is significantly distorted by the resonance of the parasitic inductance L1 and the parasitic capacitance C1 of the terminal resistor. This output waveform “ii” is problematic in that it can greatly influence the threshold level of the pulse signals. In this example, pulses having apparent frequency ft of about 1 GHz cannot be transmitted in good shape under repetition frequency f of 200 MHz.
Referring now to FIG. 3A, the same terminal resistor as in FIGS. 1A and 2A is connected to the starting end of the same bus T1. In operation, the bus is supplied with a pulse “i” having base voltage V1=0 Volt, peak voltage V2=3.3 Volts, rise time Tr=100 ps, fall time Tf=100 ps, pulse width Pw=400 ps, and pulse period Per=1 ns. Its output waveform “ii” is observed at the terminal end of the bus T1. The repetition frequency f of the pulse is 1 GHz. The apparent frequency ft is determined from the transition time as follows;ft=0.35/(100 ps×0.8)≈5 GHz.
FIG. 3B shows the input and the output waveforms “i” and “ii”, respectively. It is seen in the figure that the output waveform “ii” is delayed from the input waveform “i” by the transmission delay time Tpd (1.5 ns) of the bus T1, and is even more distorted by the parasitic inductance L1 and capacitance C1 of the terminal resistor as compared with the waveform of FIG. 2B. Obviously, this waveform “ii” cannot be used as a signal, since the waveform is disastrously distorted, badly affects the threshold level. Thus, under this condition where the repetition frequency f=1 GHz and apparent frequency ft≈5 GHz associated with the transition time, the bus completely fails to transmit the signal.
It is seen from the results of simulations shown in FIGS. 1A–3B, that the distortion of the output waveform “ii” of a pulse increases with the repetition frequency f and the apparent frequency ft associated with the transition time of the pulse. These simulations manifest that the output waveform “ii” is influenced by the parasitic inductance L1 and the parasitic capacitance C1 of the terminal resistor itself, even if the resistance of the terminal resistor is impedance matched with the characteristic impedance of the bus.
A similar simulation can be performed for the bus using a terminal chip resistor which, however, has only one tenth of ordinary parasitic inductance and capacitance (L1=1 nH and C1=10 pF, FIG. 1A).
FIG. 4A illustrates such a simulation circuit, which has now a reduced parasitic inductance L1=100 pH and a reduced parasitic capacitance C1=1 pF. The rest of the parameters of the circuit are the same as the one shown in FIG. 3A.
FIG. 4B compares the input and output waveforms “i” and “ii”, respectively, observed in the simulation. It is seen in FIG. 4B that the output waveform “ii” is delayed from the input waveform “i” by the transmission delay time Tpd (1.5 ns) of the bus T1, but has substantially the same waveform as the input waveform with little distortion.
Thus, it can be said that pulses can be successfully transmitted through a bus even when the repetition frequency f is 1 GHz and apparent frequency ft is about 5 GHz, provided that the parasitic inductance L1 and the parasitic capacitance C1 of a chip resistor are sufficiently reduced, for example, to one tenth of their conventional values.
It is noted, however, that the terminal resistor is a chip resistor, which is a discrete part mounted on the wiring substrate to terminate the bus. Consequently, the reactance of the chip resistor, that is, parasitic inductance L1 and parasitic capacitance C1, depends on the length and the width of the chip resistor. A typical chip resistor has already small dimensions on the order of 1.0 mm×0.5 mm. It is therefore very difficult, and seemingly almost impossible, to further reduce the dimensions so that the reactance is reduced by one order as suggested by the simulation shown in FIG. 4A.
If the reactive component of a resistor, that is, L1 and C1, were sufficiently reduced by the size reduction as desired, another technical problem arises from the soldering of the resistor, because soldering induces additional reactance (e.g. 200 pH and 3 pF).